As continued semiconductor scaling faces difficulties at device dimensions approaching atomic scale, three-dimensional device integration offers a method of increasing semiconductor devices within a circuit. In three-dimensional integration, a plurality of semiconductor chips is vertically stacked to provide integration of semiconductor devices beyond a single semiconductor chip.
One method of providing electrical connection between adjoining semiconductor chips is “flip chip” technology in which an array of solder balls are employed between two adjoined semiconductor chips that are vertically stacked face to face. However, flip chip technology provides electrical connection between only two vertically stacked semiconductor chip.
Another method of providing electric connection between a plurality of semiconductor chips employs through substrate vias (TSVs) that are formed through the substrate of a semiconductor chip. Typically, the TSVs extend from a line-level metal wiring structure, which is typically a first metal wiring level in a metal interconnect structure, to a bottom surface of a semiconductor chip. In conjunction with an array of solder balls, such as C4 balls, formed on top of the metal interconnect structure above the semiconductor substrate, the TSVs provide an electrical connection path through the semiconductor chip. Unlike flip chip technology, more than two semiconductor chips may be vertically stacked employing the TSVs and arrays of solder balls.
Referring to FIG. 1, a vertical cross-sectional view of a prior art semiconductor chip shows a semiconductor substrate 10 and a metal interconnect structure 90 formed thereupon. The semiconductor substrate 10 includes a semiconductor layer 12 comprising a semiconductor material. Semiconductor device regions 14 including various semiconductor devices are formed in upper portions of the semiconductor substrate 10 by method known in the art.
The various semiconductor devices in the semiconductor device regions 14 are electrically connected within the semiconductor chip employing substrate level contact vias 70 and line-level metal wiring structures 80 that are formed within a back-end-of-line (BEOL) dielectric layer 55 formed directly on the semiconductor substrate 10.
Electrical connection between the line-level metal wiring structures 80 and the bottom surface of the semiconductor substrate 10 is provided by through substrate vias (TSVs) 20, which extend from a bottom surface of the line-level metal wiring structures 80 to the bottom surface of the semiconductor substrate 10. Each of the TSVs 20 are formed through the entire thickness of the semiconductor substrate 10, hence the name “through substrate vias.”
To form the TSVs 20, a lower portion of the BEOL dielectric layer 55 is deposited on the semiconductor substrate 10, followed by patterning of through substrate trenches in the lower portion of the BEOL dielectric layer 55 and the entire thickness of the semiconductor substrate 10, as well as via holes in the lower portion of the BEOL dielectric layer 55 extending to semiconductor devices on the top surface of the semiconductor device regions 14. The through substrate trenches are filled with a conductive material such as tungsten and planarized to form the TSVs 20. The via holes are also filled to form the substrate level contact vias 70.
An upper portion of the BEOL dielectric layer 55 is thereafter deposited on the lower portion of the BEOL dielectric layer 55. Patterned areas of the upper portion of the BEOL dielectric layer 55 are recessed and filled with metal by plating. The plated metal is planarized to form the line-level metal wiring structures 80.
A horizontal cross-sectional view of a portion of the prior art semiconductor chip in FIG. 1 along the plane X-X′ is shown in FIG. 2, which shows cheesing holes formed in a line-level metal wiring structures 80. The cheesing holes, which have a square shape, are filled with the dielectric material of the BEOL dielectric layer 55. Formation of the cheesing holes is effected by preventing recessing of a plurality of isolated square areas within a large recessed area during the patterning of the upper portion of the BEOL dielectric layer 55, thereby placing isolated portions of the BEOL dielectric layer 55 with the line-level metal wiring structures 80. The resulting line-level metal wiring structures 80 contain square areas containing an insulator material, i.e., the material of the BEOL dielectric layer 55, thereby forming a pattern of cheesing holes.
The cheesing holes are necessary to prevent “dishing” of a large metal area during chemical mechanical planarization (CMP), in which a center portion of a large area metal structure becomes thinner relative to the thickness of small area metal structures interspersed with an insulator material, i.e., the material of the BEOL dielectric layer 55. The placement of the cheesing holes prevents such dishing during CMP. To maximize the effect of the cheesing holes for preventing dishing, the cheesing holes are randomly scattered throughout the entirety of a large contiguous metal area irrespective of the pattern of any structure located underneath or above.
Some of the cheesing holes thus overlap with the TSVs 20, thereby reducing the contact area between the TSVs 20 and the line-level metal wiring structures 80. Since only a fraction of the contact area between the TSVs 20 and the line-level metal wiring structures 80 is available for current conduction, the current carrying capability through the TSVs 20 is limited by the overlap area between the TSVs 20 and the line-level metal wiring structures 80. The limited current carrying capability adversely impacts the performance of the prior art semiconductor chip.
Furthermore, one of the difficulties of the prior art semiconductor chip is that a seam 19 is formed at the center of a top surface of each TSV 20. Formation of the seam 19 is an inherent consequence of the method employed to form the TSVs 20 since the conductive material is deposited on the sidewalls of the through substrate trench first, and the center portion of each TSV 20 is filled last so that a seam extends along the center of each TSV 20 through the entire height of the TSV 20, i.e., from the top surface of each TSV 20 to the bottom surface of the TSV 20 that is substantially coplanar with the bottom surface of the semiconductor substrate 10.
The seams 19 at the center of the top surface of the TSVs 20 may have an adverse, and potentially devastating, effect on the structural integrity and reliability of the TSVs 20 since a plating solution may flow through the seam 19 during a plating process that forms the line-level metal wiring structures 80, which typically comprise copper, and kept within the volume of the seams 19 even after the plating processing step. The residual plating solution in the seams 19 may induce slow corrosion of the TSVs 20 so that the resistance of the TSVs 20 increases in time.
FIG. 2 also shows the locations of TSVs 20 that underlie the line-level metal wiring structures 80 in thick dotted lines and the locations of the seams 19 within each of the TSVs 20 in thin dotted lines. Since the prior art semiconductor chip is formed without regard to the relative location of the cheesing holes, which is represented by the square areas filled with the material of the BEOL dielectric layer 55, and the TSVs 20 or the seams 19 in each of the TSVs 20, a significant portion of the seams 19 directly underlies the BEOL dielectric layer 55. During a plating process, therefore, the plating solution flows into the exposed portions of the seams 19. As discussed above, the plating solution is trapped in the seams 19 of the TSVs 20, and causes degradation of performance and/or reliability problem of the TSVs 20 during the lifetime of the semiconductor chip.
In view of the above, there exists a need for a semiconductor structure that enhances performance and reliability of through substrate vias (TSVs) in a semiconductor substrate.